1. Field of the Invention
The present invention relates to solid state devices and, more specifically, to a static random access memory having dual read port functionality.
2. Description of the Prior Art
One of the most important components in a computer is the memory. Every time a computer is started up, programs are loaded into memory. The memory into which these programs are loaded is called RAM, an acronym for Random Access Memory. It is from the RAM that most programs perform their functions and operate to give the user the required results. Most RAM memory is housed in chips or integrated circuits (IC's). There are several types of RAM. The two most common types are DRAM and SRAM.
A typical CMOS (complementary metal oxide silicon) SRAM cell (i.e., a memory unit that stores a single bit of data) has an inherent structure that generates a data output and a complement output. These outputs can have only one of two values: a “0” or a “1.” The complement output is a value that is opposite the data output. For example, if the data output is a “1” then the complement output is a “0,” similarly, if the data output is a “0” then the complement output is a “1.”
Many computers employ a cache to store instructions immediately prior to their execution by the computer's processor. A cache typically includes an SRAM that receives computer instructions from a slower memory and stores the instructions for subsequent use by the processor. When an instruction is passed from the cache to the processor, the processor is said to execute a load from the cache.
High capacity computer processors with a relatively wide instruction issue width (e.g., 4-78 issue) are required to execute two or more load instructions per cycle. In general, this requires either two copies of an L1 cache (using one read per copy) or a two-port cache array implementation. Either case can introduce from 1.7 to 2 times the array area of a one-port cache design. Furthermore, two copies of the array will consume twice the store power of a single array, while a two-port array will slow down operation of the system because of the larger overall area requirement.
For performing writes, existing SRAM cells generally require both a true data line and a complement data line. Both lines are subsequently readable. However, only the true line is read, while the complement line goes unused.
Therefore, there is a need for a cache array that provides two read ports, while adding only a small cost in area, power and performance.